1. Field of the Invention
The present invention relates to a memory circuit in which a memory cell array having a plurality of memory cells is provided and a semiconductor device in which this memory circuit is provided, and particularly relates to a semiconductor device having a configuration in which one or more logic functions are performed using a plurality of look-up tables configured by the memory circuit.
2.Description of the Related Art
In recent years, in order to use LSI for various purposes, techniques for allowing users to freely change the configuration of the LSI has been achieved. For example, a programmable logic LSI in which a large number of logic circuits are arranged, logic functions and connection relations are set according to configuration data, and it is possible to implement various logic functions by changing the configuration data. Generally when implementing a logic function of the logic circuit, a look-up table (LUT) corresponding to the desired logic function is configured in a memory, and thereby an arbitrary logic function capable of obtaining an output corresponding to a logic input having a predetermined number of bits can be implemented.
Meanwhile, the circuit scale of the programmable logic LSI is increased, a problem arises that the reconfiguration takes long time, and therefore a configuration of the programmable logic LSI is proposed in which the reconfiguration can be completed in a short time by implementing a large scale memory such as DRAM (for example, see Japanese Patent Laid-Open No. Hei 10-285014). According to a configuration disclosed therein, the entire configuration data is written to an memory element using DRAM or the like, and the configuration data is transferred to a configuration memory in a logic element, so as to achieve high-speed reconfiguration.
However, according to the above conventional configuration, since the look-up table is configured in the configuration memory, data of the look-up table written to the memory element needs to be transferred to the configuration memory, and therefore rapid reconfiguration is hindered. Then, when the memory element is used as a work RAM, a special purpose bus for connecting to the logic element is required, which causes an increase in chip area. Further, since connection information is stored in the configuration memory as well as logic information, access efficiency of the logic function is reduced. In this manner, according to the conventional configuration, even when a changeable look-up table for implementing the logic function is configured in a large scale memory circuit such as DRAM, it is difficult to utilize the look-up table effectively.